SCM, v1.2, Configurations

The Small Computer Monitor supports a range of hardware and options. These are determined at compile time and are identified by a configuration code. The current configurations are listed below.

Only a few of these have been ported from SCM v1.0/1.1 to SCM v1.2

Config.DescriptionROMRAM
00Complete custom build
C1Z80sc, standard ROM
SCM, BASIC, CP/M loader
Maintained by SCCousins
1 bank
of 32k
32k or
64k paged
E1External OS = CP/M
> incomplete <
Maintained by SCCousins
n/an/a
E2External OS = RomWBW
> incomplete <
Maintained by SCCousins
n/an/a
F1SC118/SC516, standard ROM
SCM, BASIC, CP/M loader
Maintained by SCCousins
1 bank
of 32k
32k or
64k paged
F2SC518/SC519, standard ROM
SCM, BASIC, CP/M loader
Maintained by SCCousins
1 bank
of 32k
32k or
64k paged
J1SC126 ColecoVision game
Maintained by JBLangston
512k
Z180 MMU
512k
Z180 MMU
L1LiNC80 SBC1, standard ROM
SCM, BASIC, CP/M loader
Maintained by SCCousins
and Jon Langseth
2 banks
of 16k
48k or
64k paged
M1SC126 CP/M style COM
executable
Maintained by SCCousins
n/an/a
M2SC130 CP/M style COM
executable
Maintained by SCCousins
n/an/a
M3SC131 CP/M style COM
executable
Maintained by SCCousins
n/an/a
P1Z80 Playground
> incomplete <
Maintained by John Squires
1 bank
of 16k
48k or
64k paged
R1RC2014, official image 9
SCM only
Maintained by SCCousins
1 bank
of 8k
32k
no paging
R2RC2014
SCM and BASIC
Maintained by SCCousins
1 bank
of 16k
48k
no paging
R3RC2014
SCM, BASIC, CP/M loader
Maintained by SCCousins
1 bank
of 32k
32k or
64k paged
R4RC2014, official image 88
SCM, BASIC, CP/M loader
Maintained by SCCousins
1 bank
of 16k
32k or
64k paged
S1SC101, standard ROM
SCM, BASIC, CP/M loader
Maintained by SCCousins
1 bank
of 8k
32k or
64k paged
S2SC114, standard ROM
SCM, BASIC, CP/M loader
Maintained by SCCousins
1 bank
of 32k
32k or
64k paged
S3SC108, standard ROM
SCM, BASIC, CP/M loader
Maintained by SCCousins
1 bank
of 32k
32k or
64k paged
S4SC111, Z180 CPU
SCM, BASIC, CP/M loader
Maintained by SCCousins
1 bank
of 32k
32k or
64k paged
S5SC111+SC119, Z180 system
SCM, BASIC, CP/M loader
Maintained by SCCousins
512k
Z180 MMU
512k
Z180 MMU
S6SC126, Z180 Motherboard
SCM, BASIC, CP/M loader
Maintained by SCCousins
512k
Z180 MMU
512k
Z180 MMU
T1Tom’s SBC revision C
SCM, BASIC, CP/M loader
Maintained by SCCousins
1 bank
of 16k
48k or
84k paged
Z1Z280RC by Bill Shen
Maintained by Bill Shen
Z?Z80SBC64 by Bill Shen
Maintained by Bill Shen
Z8ZORAk Mothership
> incomplete <
Maintained by SCCousins
1 bank
of 32k
32k
no paging

Notes

S4
This configuration is designed as a stepping stone from a working Z80 based RC2014 to a Z180 processor. Simply replace the Z80 CPU with a Z180 CPU and install this version of SCM. All I/O is provided by the existing external hardware (not the Z180) and any required memory management is also provided by existing external hardware.

S5
This configuration is used when a complete Z180 design is required. Z180 internal peripherals, such as serial, are used instead of external ones.

Supported Hardware

The following hardware is specifically supported, and used, by SCM. Other hardware may also exist in the system, but SCM does not provide support or use it. However, software loaded and run from SCM might make use of such hardware.

Config.Supported hardware
C1<TODO>
E1Any CP/M system
E2Any RomWBW system
F1
v1.2.0
Z80 CPU (eg. Z84C00xx)
SIO #1 at 0x80 (eg. Z84C4xxx)
SIO #2 at 0x84 (eg. Z84C4xxx)
CTC #1 at 0x88 (eg. Z84C30xx)
CTC #2 at 0x8C (eg. Z84C30xx)
ACIA #1 at 0x80 (eg. 68B50)
Bit-bang serial port at 0x20 + 0x28
Status LED at 0x08
Digital I/O at 0x00
Compact Flash at 0x10 for loading CP/M
F1
v1.2.1
Z80 CPU (eg. Z84C00xx)
SIO #1 at 0x80 (eg. Z84C4xxx)
SIO #2 at 0x84 (eg. Z84C4xxx)
CTC #1 at 0x88 (eg. Z84C30xx)
CTC #2 at 0x8C (eg. Z84C30xx)
ACIA #1 at 0xA2 (eg. 68B50)
ACIA #2 at 0xA4 (eg. 68B50)
Bit-bang serial port at 0x20 + 0x28
CF Card at 0x90 for loading CP/M
Diagnostic LEDs and digital I/O at 0xA0
Status LED at 0x08
F2
v1.2.1
Z80 CPU (eg. Z84C00xx)
SIO #1 at 0x80 (eg. Z84C4xxx)
SIO #2 at 0x84 (eg. Z84C4xxx)
CTC #1 at 0x88 (eg. Z84C30xx)
CTC #2 at 0x8C (eg. Z84C30xx)
ACIA #1 at 0xA2 (eg. 68B50)
ACIA #2 at 0xA4 (eg. 68B50)
CF Card at 0x90 for loading CP/M
Diagnostic LEDs and digital I/O at 0xA0
Status LED at 0x08
J1SC126 with JBLangston video module
L1Z80 CPU (eg. Z84C00xx)
SIO at 0x00 (eg. Z84C42xx)
CTC at 0x08 (eg. Z84C30xx)
Digital I/O at 0x30
M1SC126 (as S6)
M2SC130
M3SC131
P1Z80 CPU
> incomplete <
R1 to R4See SCM v1.0
S1Z80 CPU(eg. Z84C00xx)
> incomplete <
S2Z80 CPU (eg. Z84C00xx)
Z80 SIO #1 (rc) at 0x80 (eg. Z84C4xxx)
Z80 SIO #1 at 0x80 (eg. Z84C4xxx)
Z80 SIO #2 (rc) at 0x84 (eg. Z84C4xxx)
Z80 SIO #2 at 0x84 (eg. Z84C4xxx)
SCC #1 @ 0x00? (eg. Z85C50xx)
SCC #1 @ 0x20? (eg. Z85C50xx)
Z80 CTC #1 at 0x88 (eg. Z84C30xx)
Z80 CTC #2 at 0x8C (eg. Z84C30xx)
ACIA #1 at 0x80 (eg. 68B50)
ACIA #2 at 0xA0? (eg. 68B50)
Bit-bang serial port at 0x20 + 0x28
Status LED at 0x08
Digital I/O at 0x00
Compact Flash at 0x10 for loading CP/M
S3Z80 CPU (eg. Z84C00xx)
ACIA #1 at 0x80 (eg. 68B50)
ACIA #2 at 0x40 (eg. 68B50)
SIO #1 at 0x80 (eg. Z84C42xx)
CTC #1 at 0x88 (eg. Z84C30xx)
Digital I/O at 0x00
Compact Flash at 0x10 for loading CP/M
S4Z180 CPU (eg. Z8S180xx)
ACIA #1 at 0x80 (eg. 68B50)
ACIA #2 at 0x40 (eg. 68B50)
SIO #1 at 0x80 (eg. Z84C42xx)
CTC #1 at 0x88 (eg. Z84C30xx)
Digital I/O at 0x00
Compact Flash at 0x10 for loading CP/M
S5Z180 CPU (eg. Z8S180xx)
Z180 internal timer (for idle events)
Z180 asynchronous serial ports
Digital I/O at 0x00
Compact Flash at 0x10 for loading CP/M
S6Z180 CPU (eg. Z8S180xx)
Z180 internal timer (for idle events)
Z180 ASCI at 0xC0
Z80 SIO #1 (rc) at 0x80 (eg. Z84C4xxx)
Z80 SIO #1 at 0x80 (eg. Z84C4xxx)
Z80 SIO #2 (rc) at 0x84 (eg. Z84C4xxx)
Z80 SIO #2 at 0x84 (eg. Z84C4xxx)
SCC #1 @ 0x00? (eg. Z85C50xx)
SCC #1 @ 0x20? (eg. Z85C50xx)
Z80 CTC #1 at 0x88 (eg. Z84C30xx)
Z80 CTC #2 at 0x8C (eg. Z84C30xx)
ACIA #1 at 0x80 (eg. 68B50)
ACIA #2 at 0xA0? (eg. 68B50)
Digital I/O at 0x00
Compact Flash at 0x10 for loading CP/M
Status / self-test LEDs at 0x0D
T1Tom’s SBC version C
Z1 Bill’s Z280RC
Z8Z80 CPU (eg. Z84C00xx)
Z80 SIO #1 (rc) at 0x80 (eg. Z84C4xxx)
Z80 SIO #1 at 0x80 (eg. Z84C4xxx)
Z80 SIO #2 (rc) at 0x84 (eg. Z84C4xxx)
Z80 SIO #2 at 0x84 (eg. Z84C4xxx)
SCC #1 @ 0x00? (eg. Z85C50xx)
SCC #1 @ 0x20? (eg. Z85C50xx)
Z80 CTC #1 at 0x88 (eg. Z84C30xx)
Z80 CTC #2 at 0x8C (eg. Z84C30xx)
ACIA #1 at 0x80 (eg. 68B50)
ACIA #2 at 0xA0? (eg. 68B50)
Digital I/O at 0x00?

Hardware Identification Codes

These are hardware identifiers used within SCM and returned as part of the SCM version details. If the configuration supports more than one hardware design then the hardware identification code should be zero (unknown).

Config.CNAMEIDHardware
0#<unknown>0Unknown or custom
C1SC121121SC121 (Z80sc)
E1CPM0Any CP/M system
E2RomWBW0Any RomWBW system
F1
v1.2.0
SC118118SC118 (Z50Bus)
F1
v1.2.1
Z50Bus13SC516, SC118 (Z50Bus)
F2
v1.2.1
Z50Bus13SC519 (Z50Bus)
J1Coleco?SC126+ColecoVision
L1LiNC805LiNC80 SBC1
M1SC126126SC126 (RC2014+ bus)
M2SC130130SC130 (RC2014 bus)
M3SC131131SC131
P1Z80PG11Z80 Playground
R#RC20143RC2014 official systems
S1SC101111SC101 (RC2014 bus)
S2SC114114SC114 (RC2014 bus)
S3SC108108SC108 (RC2014 bus)
S4Z180111SC111 (RC2014+ bus)
S5Z180_RC12SC111+119 (RC2014+)
S6SC126126SC126 (RC2014+ bus)
T1TomsSBC6SBC version C
W1SCWorkshop1Simulated
Z1Z280RC7Z280RC
Z2Z80SBC649Z80SBC64
Z8ZORAk10ZORAk Mothership
SCDevKit012

CNAME is the configuration name (maximum of 11 characters)

Hardware Flags Summary

Hardware identified by SCM is indicated by the flags described below. These flags are returned as part of the SCM version details. Due to the greater range of hardware now supported, this method is no longer adequate to uniquely identify all of the console devices.

Flag bitHardware for SCM configurations R# and S#
Bit 0ACIA #1 at 0x80
Bit 1SIO #1 at 0x80
Bit 2ACIA #2 at 0x40
Bit 3Bit-bang serial
Bit 4CTC #1 at 0x88
Bit 5SIO #2 at 0x84
Bit 6CTC #2 at 0x8C
Bit 7Other console interface (eg. Z180 serial)

Homebrew 8-bit retro computing