SC119, v1.0, Circuit Explained

The SC119, Z180 Memory module includes the two 512k byte Flash chips and one 512k byte RAM chip. In normal operation, only one of the Flash chips can be used, meaning the module effectively provides 1M byte of memory (512k Flash, plus 512k RAM).

To create a minimal computer system, a Z180 CPU module must be added, together with a backplane to connect the two modules.

C1 to C4

These capacitors provide power supply decoupling (or bypass). The fast switching in digital circuits creates spikes on the power supply lines which are suppressed with decoupling capacitors placed at key points on the circuit board.


This capacitor helps prevent the supply voltage from dipping when current surges occur.

JP1 and JP2

Jumper 1 allows Flash chip U1’s write enable input to be connected to either Vcc (5 volts) or the CPU’s write output (/WR). Jumper 2 provides the same function for Flash U2.

When the Flash chip’s write enable input is connected to Vcc, the Flash chip will never get a write enable signal and thus the memory is protected against being changed. When connected to the CPU’s write output, it is possible to write to the Flash chip.

Writing to the Flash chip is unlikely to happen by accident due to the software requirements. However, for peace of mind it is generally best to disable writing with this jumper.


When a jumper shunt is fitted to this header, Flash U1 is selected. When the shunt is not fitted, Flash U2 is selected.

Header pins P2 allow an external switch to be used instead of a jumper shunt. In addition, it is possible to connect and external control signal to this header to enable software selection of the current Flash chip. By this method it is theoretically possible to access both Flash chips.

The external signal is a simple digital level, low for U1 and high for U2. There is a pull up resistor on this signal, so it defaults to high when not connected.

U1 and U2

These are 512k byte Flash memory chips.


This is a 512k byte static RAM chip.


U4 is a dual 2-to-4 line decoder. This handles address decoding for the memory. The Z180 has a 1M byte memory map. The bottom 512k bytes is decoded to the currently selected Flash chip, while the top 512k bytes is always the 512k byte RAM chip.

A 74AHCT139 is specified instead of the usual HCT series component. The AHCT part is faster, thus increasing the chances of being able to run the system at a higher clock speed than the default 18.432 MHz. In fact, the Z180’s software selectable clock multiplier could be used to overclock the system to 36.864 MHz. However, I must stress that this is NOT in any way guaranteed to work.


This is the RC2014 bus connector.


This is a header to connect an optional external flash chip select switch, as described above.

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